1. Field of the Invention
This invention relates to an improved integrated circuit, decoupling capacitor and, more particularly, to an integrated circuit, decoupling capacitor that reduces integrated circuit chip rejection due to manufacturing defects in the decoupling capacitor.
2. Description of the Prior Art
In the design of logic circuits, a decoupling capacitor is generally used to isolate the logic circuit from rapid changes in the power supply voltage, so-called power supply bounce. In a typical circuit design, as shown in FIG. 1, the decoupling capacitor is wired directly to the power supply and can cause a failure of an entire chip if only one decoupling capacitor develops a short circuit.
In a conventional integrated circuit process, the decoupling capacitor is a composite made up of layers of thin dielectric films deposited on top of a heavily doped N+ region. In order to achieve a large capacitance, the thickness of the dielectric films is extremely thin (e.g., 60 .ANG. oxide/100 .ANG. nitride) and the capacitor area has to be relatively large. In the process of manufacturing integrated circuits that include such decoupling capacitors, defects, such as a pin hole for example, in the thin, dielectric capacitor films are a common occurrence. Since, as shown in FIG. 1, the decoupling capacitor is connected directly to the power supply, a short in a single decoupling capacitor can result in a failure of the entire chip.